Phase frequency detector

ABSTRACT

Provided is a phase frequency detector for use in a phase locked loop (PLL) or a delay locked loop (DLL), the phase frequency detector including: an UP signal output unit having a first stage operated according to a reference clock delayed by a predetermined time and a reset signal, a second stage operated according to the reference clock and an output of the first stage, and an inverter for inverting an output of the second stage; a DOWN signal output unit having: a first stage operated according to an outer clock delayed by a predetermined time and the reset signal, a second stage operated according to the outer clock and an output of the first stage, and an inverter for inverting an output of the second stage; and a logic gate logically combining the output of the second stage of the UP signal output unit and the output of the second stage of the DOWN signal output unit to generate the reset signal, thereby a phase range of the input signal with which an effective control signal can be obtained is wide so that low power consumption and low noise characteristics can be obtained due to fast phase lock, low power consumption of a dynamic logic, and fast signal transmission.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to and the benefit of Korean PatentApplication No. 2004-90672, filed on Nov. 9, 2004, the disclosure ofwhich is incorporated herein by reference in its entirety.

BACKGROUND

1. Field of the Invention

The present invention relates to a phase frequency detector for use in aphase locked loop (PLL) or a delay locked loop (DLL) and, morespecifically, to a phase frequency detector capable of operating at ahigh frequency and having fast phase lock, low power consumption, andlow noise characteristics.

2. Discussion of Related Art

A phase locked loop (hereinafter, referred to as PLL), which is afrequency feedback circuit that generates any frequency according to apredetermined clock signal, is used for a frequency synthesizer and adata processor, etc.

In general, the PLL includes a reference frequency generator, a voltagecontrolled oscillator (VCO), a frequency divider for dividing afrequency output from the VCO, a phase frequency detector (hereinafter,referred to as PFD) for receiving the reference frequency and thedivided frequency to detect a phase, a charge pump for receiving a phasedifference signal output from the PFD, and a loop filter for removing ahigh frequency component of a signal output from the charge pump. Anoutput frequency of the VCO is controlled according to the voltageoutput through the loop filter.

The PFD receives the reference frequency and the divided frequency tooutput UP and DOWN signals. Here, the phase difference between twofrequencies is represented by a difference of a pulse width of the UPand DOWN signals. When different frequencies are input, the frequencydifference corresponds to a difference of the average pulse width of theUP and DOWN signals.

As shown in FIG. 1, the typical PFD includes flip-flops 1 and 2 forreceiving a reference frequency clock CKref and a divided frequencyclock CKout, respectively, to output the UP and DOWN signals; and a NANDgate 3 for logically combining the UP and DOWN signals to generate areset signal for resetting the flip-flips 1 and 2.

Referring to FIG. 2, the UP signal becomes “1” at a rising edge of thereference frequency clock CKref and the DOWN signal becomes “1” at arising edge of the divided frequency clock CKout. When both UP and DOWNsignals become “1”, the flip-flops 1 and 2 are reset by the output ofthe NAND gate 3 so that both UP and DOWN signals become “0”. The UPsignal which is the phase difference of the CKref and the CKout, istransferred to the charge pump so that the output frequency of the VCOis increased or decreased.

In the PFD used for the PLL, delay means is generally inserted into areset path to prevent a dead zone such that certain duration pulses aresimultaneously output through UP and DOWN signal output terminals whenphases of two input clocks CKref and CKout are matched. The charge pumpconnected to the output stage of the PFD requires more than a certainnumber of duration pulses for an exact switching operation so that theextremely small delay means is not allowed in the reset path. Typically,a size of the delay means is typically determined such that the pulseduration time output through the UP and DOWN signal output terminals is300 ps or more.

As the pulse duration output through the UP and DOWN signal outputterminals become longer, Δ in FIG. 3 becomes larger. In this case, whenthe UP and DOWN signals are output in a reversed direction rather thanthe fixed direction, a time required for phase lock becomes longer. Inaddition, as the frequencies of the input clocks CKref and CKout becomehigher, a ratio of the pulse width for preventing the dead zone to thecompared clock period becomes larger. Therefore, Δ becomes larger andthe operation speed of the PFD reaches a limitation. When Δ is more thanπ, the phase lock is not guaranteed. [Ref. Mansuri M. etc. “Fastfrequency acquisition phase-frequency detectors for Gsamples/sphase-locked loops”, Solid-State Circuits, IEEE Journal of Vol. 37, pp1331-1334, 2002. 10.].

Mansuri M. etc. proposed a phase frequency detector arranged as in FIG.4 to improve the problems. FIG. 5 is a waveform showing the operationcharacteristics of the phase frequency detector shown in FIG. 4, whichshows that the time for locking phase becomes shorter.

When a phase error is close to 2π, pulses P_(ref) and P_(out) delayed byan inverter remain high during a predetermined time after a falling edgeof the reset signal RST so that right UP and DOWN signals are output.When the predetermined time is t1, an ON current of transistors N1, N2,N3 or N4, N5, N6 connected in series should be sufficient to change astate of the latch to output the UP and DOWN signals as high statesduring t1 time. For the operation of the fast phase lock, the state ofthe latch should be changed even when t1 is extremely short. Therefore,channel widths of the transistors N1, N2, N3 or N4, N5, N6 should belarge so that it is difficult to reduce power consumption.

SUMMARY OF THE INVENTION

The present invention is directed to a phase frequency detector capableof operating at a high frequency and having fast phase lock, low powerconsumption, and low noise characteristics.

One aspect of the present invention is to provide a phase frequencydetector including: an UP signal output unit having a first stageoperated according to a reference clock delayed by a predetermined timeand a reset signal, a second stage operated according to the referenceclock and an output of the first stage, and an inverter for inverting anoutput of the second stage; a DOWN signal output unit having: a firststage operated according to an outer clock delayed by a predeterminedtime and the reset signal, a second stage operated according to theouter clock and an output of the first stage, and an inverter forinverting an output of the second stage; and a logic gate logicallycombining the output of the second stage of the UP signal output unitand the output of the second stage of the DOWN signal output unit togenerate the reset signal.

The first stage of the UP signal output unit includes: first and secondtransistors connected in series between a power supply voltage and anoutput node; and a third transistor connected between the output nodeand ground, and wherein the reset signal is input to gates of the firstand third transistors, and the delayed reference clock is input to agate of the second transistor.

The second stage of the UP signal output unit includes: a firsttransistor connected between a power supply voltage and an output node;and second and third transistors connected in series between the outputnode and ground, and wherein the reference clock is input to a gate ofthe second transistor, and gates of the first and third transistors areconnected to the output node.

The phase frequency detector may further include: a fourth transistorconnected between the output of the second stage and a connection of thesecond transistor and the third transistor, wherein the fourthtransistor is operated according to the delayed reference clock.

The first stage of the DOWN signal output unit includes: first andsecond transistors connected in series between a power supply voltageand an output node; and a third transistor connected between the outputnode and ground, and wherein the reset signal is input to gates of thefirst and third transistors, and the delayed outer clock is input to agate of the second transistor.

The second stage of the DOWN signal output unit includes: a firsttransistor connected between a power supply voltage and an output node;and second and third transistors connected in series between the outputnode and ground, and wherein the outer clock is input to a gate of thesecond transistor, and gates of the first and third transistors areconnected to the output node.

The phase frequency detector may further include: a fourth transistorconnected between the output of the second stage and a connection of thesecond transistor and the third transistor, wherein the fourthtransistor is operated according to the delayed outer clock.

The predetermined time may be set to be shorter than a time from arising edge of a later input clock between the reference clock and theouter clock to a falling edge of the reset signal.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features of the present invention will be describedin reference to certain exemplary embodiments thereof with reference tothe attached drawings in which:

FIG. 1 is a circuit diagram for explaining a conventional phasefrequency detector;

FIG. 2 is a timing diagram for explaining the operation of FIG. 1;

FIG. 3 is a waveform for explaining the operation characteristics ofFIG. 1;

FIG. 4 is a circuit diagram showing another example of the conventionalphase frequency detector;

FIG. 5 is a waveform for explaining the operation characteristics ofFIG. 4;

FIG. 6 is a circuit diagram for explaining a phase frequency detectoraccording to a first embodiment of the present invention;

FIG. 7 is a timing diagram for explaining the operation of FIG. 6; and

FIG. 8 is a circuit diagram for explaining a phase frequency detectoraccording to a second embodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Exemplary embodiments of the present invention will now be described indetail with reference to the accompanying drawings. The followingembodiments are provided for a thorough understanding to those skilledin the art, and a variety of modification can be made and the scope ofthe present invention is not limited to the embodiments described below.

FIG. 6 is a circuit diagram for explaining a phase frequency detectoraccording to a first embodiment of the present invention.

The phase frequency detector (PFD) of the present invention includes: anUP signal output unit 10 for receiving a reference clock CLKref and apredetermined time delayed reference clock D_CLKref; a DOWN signaloutput unit 20 for receiving an outer clock CLKout and a predeterminedtime delayed outer clock D_CLKout; and a logical gate for logicallycombining outputs of the UP signal output unit 10 and the DOWN signaloutput unit 20 to generate a reset signal RST.

The UP signal output unit 10 includes: a first stage operated accordingto the predetermined time delayed reference clock D_CLKref, delayed bydelay means D1, and the reset signal RST; a second stage operatedaccording to the reference clock CLKref and an output of the firststage; and an inverter I1 for inverting an output of the second stage.

The first stage includes transistors Mp11 and Mp12 connected in seriesbetween a power supply voltage Vcc and an output node K11 and atransistor Mn11 connected between the output node K11 and the ground,wherein the reset signal RST is input to gates of the transistors Mp1and Mn11, and the predetermined time delayed reference clock D_CLKref isinput to a gate of the transistor Mp12 through the delay means D1.

The second stage includes a transistor M13 connected between the powersupply voltage Vcc and an output node K12 and transistors Mn12 and Mn13connected in series between the output node K12 and the ground, whereinthe reference clock CLKref is input to a gate of the transistor Mn12,and gates of the transistors Mp13 and Mn13 are connected to the outputnode K11.

The inverter I1 is connected between the output node K12 and the UPsignal output terminal.

The DOWN signal output unit 20 includes: a first stage operatedaccording to the predetermined time delayed outer clock D_CLKout,delayed through delay means D2, and the reset signal RST; a second stageoperated according to the outer clock CLKout and an output of the firststage; and an inverter 12 for inverting an output of the second stage.

The first stage includes: transistors Mp21 and Mp22 connected in seriesbetween the power supply voltage Vcc and an output node K21; and atransistor Mn21 connected between the output node K21 and the ground,wherein the reset signal RST is input to gates of the transistors Mp21and Mn21, and the predetermined time delayed outer clock D_CLKout isinput to a gate of the transistor Mp22 through the delay means D2.

The second stage includes: a transistor Mp23 connected between the powersupply voltage Vcc and an output node K22; and transistors Mn22 and Mn23connected in series between the output node K22 and the ground, whereinthe outer clock CLKout is input to a gate of the transistor Mn22, andgates of the transistors Mp23 and Mn23 are connected to the output nodeK21.

The inverter 12 is connected between the output node K22 and the DOWNsignal output terminal.

The delay means D1 and D2 may include, for example, an even number ofinverters, and the logic gate 30 may include, for example, a NOR gate tologically combine the signal output through the output nodes K12 and K22to generate the reset signal RST.

In the PFD of the present invention arranged as described above, thereference clock CLKref is delayed by td1 by the delay means D1, and incase of td1<td5, it has the operation characteristics as shown in FIG.5. In other words, the delay time td1 is set to be shorter than a timetd5 from a rising edge of the later input clock of the reference clockCLKref and the outer clock CLKout to a falling edge of the reset signalRST. Here, td1=td5−(δ/2π)/fclk and the smaller δ is preferable. However,it is desirable that td1 is determined to have some margin of δ inconsideration of characteristics such as processing conditions andtemperature.

Referring to FIG. 7, td2 refers to a delay time taken from the gate ofthe transistor Mn12 to the UP signal output terminal, and td3 refers toa delay time taken from the input of the reset signal RST to the UPsignal output terminal. As for td3, td6 refers to a delay time takenfrom the input of the reset signal to the UP signal output terminal, buta rising edge and a falling edge are converse.

td4 refers to a pulse width for preventing dead zone, which isdetermined by a delay time of the logic gate 30 located in the resetpath. In FIG. 7, about 3 periods of phase is compared, in whichoperation at the rising edge of the second clock CLKref is differentfrom that in FIG. 3. For this portion, a phase difference between thereference clock CLKref and the outer clock CLKout exists in range of2π−Δ<Δ Φ <2π−δ, in which a missing edge does not occur and the UP signalbecomes high earlier than the DOWN signal, in the same manner shown; inFIG. 5. In the third period with ΔΦ≧2π−δ, the DOWN signal becomes highfirst.

Assuming that the loads connected to the UP and DOWN signal outputterminals have the same amplitude and the same rising and falling edges,the PFD of the present invention shown in FIG. 7 has smaller powerconsumption compared to the conventional PFD shown in FIG. 4. In case ofthe conventional PFD shown in FIG. 4, in order to change a state of alatch, current driving capability of the transistors P1 and P2 andcurrent driving capabilities of the transistors N1, N2, N3 or N3, N4, N5connected in series should be larger than that of a positive feedback ofthe latch. Therefore, since the channel width of the transistor shouldbe much larger than that shown in FIG. 7, more power is consumed todrive the PFD of FIG. 4 at the same operating frequency.

Since the PFD of the present invention arranged in FIG. 6 includes adynamic logic, there is little room that jitter occurs. In FIG. 7, thephase difference is indicated by a duration difference between the UPsignal and the DOWN signal. A variation of the td2 difference and avariation of the td6 difference for the UP signal output unit 10 and theDOWN signal output unit 20 are indicated by a jitter, so that when thePFD of the present invention is applied, the noise characteristic of thePLL is improved.

The delay time td2 taken from the input of the reference clock CLKrefand the UP signal output is equal to a sum of a time for the transistorMn12 to discharge precharged charges in the input stage of the inverterI1 and a delay time of one inverter. Therefore, the delay time td2 isextremely short so that it may be differ from a delay time taken fromthe input of the outer clock CLKout to the DOWN signal output. Inaddition, the delay time td6 taken from the input of the reset signalRST to the UP signal output is equal to a sum of a time for thetransistor Mn11 to discharge precharged charges in the gate of thetransistor Mp13 and Mn13 and a time for the transistor Mp13 to prechargethe gate of the inverter I1. The delay time td6 is also extremely shortso that it may be differ from a delay time taken from the input of thereset clock RST to the DOWN signal output.

However, for the conventional PFD shown in FIG. 4, the path from theinput to the output is longer and the state change speed of the latch isslower than that for a case where the charges of the precharged gate aredischarged. Therefore, it will have a longer delay time and there ismore chance that the jitter occurs.

A cutoff frequency of the PFD arranged as shown in FIG. 6 is equal totd5*fclk*2π<π when a duty ratio of two input clocks is 50%. This is thesame cutoff frequency as that for the general PFD having acharacteristic shown in FIG. 3, but smaller than that for the PFD shownin FIG. 4. However, the PFD of FIG. 6 can operate at a higher frequency,as the duty ratio becomes larger. Since reference clock CLKref typicallyhas a duty ratio of 50%, a sign of the outer clock CLKout should beadjusted such that the rising edge has a higher duty ratio to ensure theoperation at the maximum frequency when used in the PLL. When the resettime is about 300 ps, td5 is about 500 ps and the cutoff frequency fclkis about 1 GHz. However, since the PFD of FIG. 6 has the samecharacteristic as that shown in FIG. 5, it is possible to have a fastphase acquisition and low power consumption and low noisecharacteristics. Therefore, it is suitable when the input frequency isless than 1 GHz.

FIG. 8 is a circuit diagram for explaining a phase frequency detectoraccording to a second embodiment of the present invention, wheretransistors Mn14 and Mn24 are added to the phase frequency detector ofFIG. 6.

The transistor Mn14 connected between the output node K12 and a node K13receives the delayed reference clock D_CLKref through a gate, and thetransistor Mn24 connected between the output node K22 and a node K23receives the delayed outer clock D_CLKout through a gate.

The PFD according to the present embodiment has the same operationcharacteristic as that of FIG. 5, and the cutoff frequency becomestd5*fclk*2π<π, which is different from that for the PFD of FIG. 6.Therefore, the cutoff frequency is twice higher than that for the PFD ofFIG. 6. This is the same cutoff frequency as that for the conventionalPFD arranged as shown in FIG. 4.

The PFD according to the present invention has almost the same powerconsumption and noise characteristic as the PFD of FIG. 6, so that ithas a better performance than the PFD of FIG. 4. However, since the PFDof FIG. 8 has two more transistors Mn14 and Mn24 that the PFD of FIG. 6,the PFD of FIG. 8 is preferably operated at a high frequency where thePFD of FIG. 6 is difficult to be operated.

As described above, a phase frequency detector of the present inventionuses a dynamic logic and a delay circuit so that the effective controlsignal can be output even when a phase difference between two clocksignals is significantly close to 360 degrees. Therefore, a phase rangeof the input signal with which the effective control signal can beobtained is wide so that high frequency operation is available and a lowpower consumption and a low noise characteristic can be achieved due toa fast phase lock, a low power consumption of the dynamic logic, and afast signal transmission.

As described above, exemplary embodiments of the present invention havebeen described with reference to the detailed description and thedrawings. Terms are used for illustration only, and should not beconstrued to limit the scope of the present invention described in theclaims. Therefore, those skilled in the art will appreciate that avariety of modifications and equivalents thereto can be made.Accordingly, the scope of the present invention will be defined to thesubject matter of the following claims.

1. A phase frequency detector comprising: an UP signal output unithaving a first stage operated according to a reference clock delayed bya predetermined time and a reset signal, a second stage operatedaccording to the reference clock and an output of the first stage, andan inverter for inverting an output of the second stage; a DOWN signaloutput unit having: a first stage operated according to an outer clockdelayed by a predetermined time and the reset signal, a second stageoperated according to the outer clock and an output of the first stage,and an inverter for inverting an output of the second stage; and a logicgate logically combining the output of the second stage of the UP signaloutput unit and the output of the second stage of the DOWN signal outputunit to generate the reset signal.
 2. The phase frequency detectoraccording to claim 1, wherein the first stage of the UP signal outputunit comprises: first and second transistors connected in series betweena power supply voltage and an output node; and a third transistorconnected between the output node and the ground, wherein the resetsignal is input to gates of the first and third transistors, and thedelayed reference clock is input to a gate of the second transistor. 3.The phase frequency detector according to claim 1, wherein the secondstage of the UP signal output unit comprises: a first transistorconnected between a power supply voltage and an output node; and secondand third transistors connected in series between the output node andthe ground, wherein the reference clock is input to a gate of the secondtransistor, and gates of the first and third transistors are connectedto the output node.
 4. The phase frequency detector according to claim3, further comprising a fourth transistor connected between the outputof the second stage and a connection point of the second transistor andthe third transistor, and operated according to the delayed referenceclock.
 5. The phase frequency detector according to claim 1, wherein thefirst stage of the DOWN signal output unit comprises: first and secondtransistors connected in series between a power supply voltage and anoutput node; and a third transistor connected between the output nodeand the ground, wherein the reset signal is input to gates of the firstand third transistors, and the delayed outer clock is input to a gate ofthe second transistor.
 6. The phase frequency detector according toclaim 1, wherein the second stage of the DOWN signal output unitcomprises: a first transistor connected between a power supply voltageand an output node; and second and third transistors connected in seriesbetween the output node and the ground, wherein the outer clock is inputto a gate of the second transistor, and gates of the first and thirdtransistors are connected to the output node.
 7. The phase frequencydetector according to claim 6, further comprising a fourth transistorconnected between the output of the second stage and a connection pointof the second transistor and the third transistor, and operatedaccording to the delayed outer clock.
 8. The phase frequency detectoraccording to claim 1, wherein the delayed reference clock and thedelayed outer clock are delayed through delay means, respectively. 9.The phase frequency detector according to claim 1, wherein thepredetermined time is set to be shorter than a time from a rising edgeof a later input clock between the reference clock and the outer clockto a falling edge of the reset signal.